Methods of forming stressed layers on FinFET semiconductor devices and the resulting devices

ABSTRACT

One method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess and forming a stress-inducing material layer above the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure, a stress-inducing material layer formed above the buried fin contact structures and a source/drain contact that extends through the stress-inducing material layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure generally relates to the fabrication ofintegrated circuits, and, more particularly, to various methods offorming stressed layers on FinFET semiconductor devices and theresulting semiconductor devices.

2. Description of the Related Art

In modern integrated circuits, such as microprocessors, storage devicesand the like, a very large number of circuit elements, especiallytransistors, are provided and operated on a restricted chip area.Immense progress has been made over recent decades with respect toincreased performance and reduced feature sizes of circuit elements,such as transistors. However, the ongoing demand for enhancedfunctionality of electronic devices forces semiconductor manufacturersto steadily reduce the dimensions of the circuit elements and toincrease the operating speed of the circuit elements. The continuingscaling of feature sizes, however, involves great efforts in redesigningprocess techniques and developing new process strategies and tools so asto comply with new design rules. Generally, in complex circuitryincluding complex logic portions, MOS technology is presently apreferred manufacturing technique in view of device performance and/orpower consumption and/or cost efficiency. In integrated circuitsincluding logic portions fabricated by MOS technology, field effecttransistors (FETs) are provided that are typically operated in aswitched mode, that is, these devices exhibit a highly conductive state(on-state) and a high impedance state (off-state). The state of thefield effect transistor is controlled by a gate electrode, whichcontrols, upon application of an appropriate control voltage, theconductivity of a channel region formed between a drain region and asource region.

To improve the operating speed of FETs, and to increase the density ofFETs on an integrated circuit device, device designers have greatlyreduced the physical size of FETs over the years. More specifically, thechannel length of FETs has been significantly decreased, which hasresulted in improving the switching speed of FETs. However, decreasingthe channel length of a FET also decreases the distance between thesource region and the drain region. In some cases, this decrease in theseparation between the source and the drain makes it difficult toefficiently inhibit the electrical potential of the source region andthe channel from being adversely affected by the electrical potential ofthe drain. This is sometimes referred to as a so-called short channeleffect, wherein the characteristic of the FET as an active switch isdegraded.

In contrast to a FET, which has a planar structure, a so-called FinFETdevice has a three-dimensional (3D) structure. FIG. 1A is a perspectiveview of an illustrative prior art FinFET semiconductor device “A” thatis formed above a semiconductor substrate B that will be referenced soas to explain, at a very high level, some basic features of a FinFETdevice. In this example, the FinFET device A includes three illustrativefins C, a gate structure D, sidewall spacers E and a gate cap layer F.The gate structure D is typically comprised of a layer of gateinsulating material (not separately shown), e.g., a layer of high-kinsulating material or silicon dioxide, and one or more conductivematerial layers (e.g., metal and/or polysilicon) that serve as the gateelectrode for the device A. The fins C have a three-dimensionalconfiguration: a height H, a width W and an axial length L. The axiallength L corresponds to the direction of current travel in the device Awhen it is operational. The portions of the fins C covered by the gatestructure D are the channel regions of the FinFET device A. In aconventional process flow, the portions of the fins C that arepositioned outside of the spacers E, i.e., in the source/drain regionsof the device A, may be increased in size or even merged together (asituation not shown in FIG. 1A) by performing one or more epitaxialgrowth processes. The process of increasing the size of or merging thefins C in the source/drain regions of the device A is performed toreduce the resistance of source/drain regions and/or make it easier toestablish electrical contact to the source drain regions. Even if an epi“merger” process is not performed, an epi growth process will typicallybe performed on the fins C to increase their physical size.

In the FinFET device A, the gate structure D may enclose both sides andthe upper surface of all or a portion of the fins C to form a tri-gatestructure so as to use a channel having a three-dimensional structureinstead of a planar structure. In some cases, an insulating cap layer(not shown), e.g., silicon nitride, is positioned at the top of the finsC and the FinFET device only has a dual-gate structure (sidewalls only).Unlike a planar FET, in a FinFET device, a channel is formedperpendicular to a surface of the semiconducting substrate so as toreduce the physical size of the semiconductor device. Also, in a FinFET,the junction capacitance at the drain region of the device is greatlyreduced, which tends to significantly reduce short channel effects. Whenan appropriate voltage is applied to the gate electrode of a FinFETdevice, the surfaces (and the inner portion near the surface) of thefins C, i.e., the vertically oriented sidewalls and the top uppersurface of the fin, form a surface inversion layer or a volume inversionlayer that contributes to current conduction. In a FinFET device, the“channel-width” is estimated to be about two times (2×) the verticalfin-height plus the width of the top surface of the fin, i.e., the finwidth. Multiple fins can be formed in the same foot-print as that of aplanar transistor device. Accordingly, for a given plot space (orfoot-print), FinFETs tend to be able to generate significantly higherdrive current density than planar transistor devices. Additionally, theleakage current of FinFET devices after the device is turned “OFF” issignificantly reduced as compared to the leakage current of planar FETs,due to the superior gate electrostatic control of the “fin” channel onFinFET devices. In short, the 3D structure of a FinFET device is asuperior MOSFET structure as compared to that of a planar FET,especially in the 20 nm CMOS technology node and beyond. The gatestructures D for such FinFET devices may be manufactured using so-called“gate-first” or “replacement gate” (gate-last) manufacturing techniques.

For many early device technology generations, the gate structures ofmost transistor elements (planar or FinFET devices) were comprised of aplurality of silicon-based materials, such as a silicon dioxide and/orsilicon oxynitride gate insulation layer, in combination with apolysilicon gate electrode. However, as the channel length ofaggressively scaled transistor elements has become increasingly smaller,many newer generation devices employ gate structures that containalternative materials in an effort to avoid the short channel effectswhich may be associated with the use of traditional silicon-basedmaterials in reduced channel length transistors. For example, in someaggressively scaled transistor elements, which may have channel lengthson the order of approximately 10-32 nm or less, gate structures thatinclude a so-called high-k dielectric gate insulation layer and one ormore metal layers that function as the gate electrode (HK/MG) have beenimplemented. Such alternative gate structures have been shown to providesignificantly enhanced operational characteristics over the heretoforemore traditional silicon dioxide/polysilicon gate structureconfigurations.

Depending on the specific overall device requirements, several differenthigh-k materials—i.e., materials having a dielectric constant, ork-value, of approximately 10 or greater—have been used with varyingdegrees of success for the gate insulation layer in an HK/MG gateelectrode structure. For example, in some transistor element designs, ahigh-k gate insulation layer may include tantalum oxide (Ta₂O₅), hafniumoxide (HfO₂), zirconium oxide (ZrO₂), titanium oxide (TiO₂), aluminumoxide (Al₂O₃), hafnium silicates (HfSiO_(x)) and the like. Furthermore,one or more non-polysilicon metal gate electrode materials—i.e., a metalgate stack—may be used in HK/MG configurations so as to control the workfunction of the transistor. These metal gate electrode materials mayinclude, for example, one or more layers of titanium (Ti), titaniumnitride (TiN), titanium-aluminum (TiAl), titanium-aluminum-carbon(TiALC), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalumnitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN),tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.

One well-known processing method that has been used for forming atransistor with a high-k/metal gate structure is the so-called “gatelast” or “replacement gate” technique. The replacement gate process maybe used when forming planar devices or 3D devices. FIGS. 1B-1Esimplistically depict one illustrative prior art method for forming anHK/MG replacement gate structure using a replacement gate technique on aplanar transistor device. As shown in FIG. 1B, the process includes theformation of a basic transistor structure above a semiconductingsubstrate 12 in an active area defined by a shallow trench isolationstructure 13. At the point of fabrication depicted in FIG. 1A, thedevice 10 includes a sacrificial gate insulation layer 14, a dummy orsacrificial gate electrode 15, sidewall spacers 16, a layer ofinsulating material 17 and source/drain regions 18 formed in thesubstrate 12. The various components and structures of the device 10 maybe formed using a variety of different materials and by performing avariety of known techniques. For example, the sacrificial gateinsulation layer 14 may be comprised of silicon dioxide, the sacrificialgate electrode 15 may be comprised of polysilicon, the sidewall spacers16 may be comprised of silicon nitride and the layer of insulatingmaterial 17 may be comprised of silicon dioxide. The source/drainregions 18 may be comprised of implanted dopant materials (N-typedopants for NMOS devices and P-type dopants for PMOS devices) that areimplanted into the substrate 12 using known masking and ion implantationtechniques. Of course, those skilled in the art will recognize thatthere are other features of the transistor 10 that are not depicted inthe drawings for purposes of clarity. For example, so-called haloimplant regions are not depicted in the drawings, as well as variouslayers or regions of silicon/germanium that are typically found in highperformance PMOS transistors. At the point of fabrication depicted inFIG. 1B, the various structures of the device 10 have been formed and achemical mechanical polishing (CMP) process has been performed to removeany materials above the sacrificial gate electrode 15 (such as aprotective cap layer (not shown) comprised of silicon nitride) so thatat least the sacrificial gate electrode 15 may be removed.

As shown in FIG. 1C, one or more etching processes are performed toremove the sacrificial gate electrode 15 and the sacrificial gateinsulation layer 14 to thereby define a gate cavity 20 where areplacement gate structure will subsequently be formed. Typically, thesacrificial gate insulation layer 14 is removed as part of thereplacement gate technique, as depicted herein. However, the sacrificialgate insulation layer 14 may not be removed in all applications.

Next, as shown in FIG. 1D, various layers of material that willconstitute a replacement gate structure 30 are formed in the gate cavity20. Even in cases where the sacrificial gate insulation layer 14 isintentionally removed, there will typically be a very thin native oxidelayer (not shown) that forms on the substrate 12 within the gate cavity20. The materials used for the replacement gate structures 30 for NMOSand PMOS devices are typically different. For example, the replacementgate structure 30 for an NMOS device may be comprised of a high-k gateinsulation layer 30A, such as hafnium oxide, having a thickness ofapproximately 2 nm, a first metal layer 30B (e.g., a layer of titaniumnitride with a thickness of about 1-2 nm), a second metal layer 30C—aso-called work function adjusting metal layer for the NMOS device—(e.g.,a layer of titanium-aluminum or titanium-aluminum-carbon with athickness of about 5 nm), a third metal layer 30D (e.g., a layer oftitanium nitride with a thickness of about 1-2 nm) and a bulk metallayer 30E, such as aluminum or tungsten.

Ultimately, as shown in FIG. 1E, one or more CMP processes are performedto remove excess portions of the gate insulation layer 30A, the firstmetal layer 30B, the second metal layer 30C, the third metal layer 30Dand the bulk metal layer 30E positioned outside of the gate cavity 20 tothereby define the replacement gate structure 30 for an illustrativeNMOS device. Typically, the replacement metal gate structure 30 for aPMOS device does not include as many metal layers as does an NMOSdevice. For example, the gate structure 30 for a PMOS device may onlyinclude the high-k gate insulation layer 30A, a single layer of titaniumnitride—the work function adjusting metal for the PMOS device—having athickness of about 3-4 nm, and the bulk metal layer 30E.

FIG. 1F depicts the device 10 after several process operations wereperformed. First, one or more etching processes were performed to removeupper portions of the various materials within the cavity 20 so as toform a recess within the gate cavity 20. Then, a gate cap layer 31 wasformed in the recess above the recessed gate materials. The gate caplayer 31 is typically comprised of silicon nitride and it may be formedby depositing a layer of gate cap material so as to over-fill the recessformed in the gate cavity and thereafter performing a CMP process toremove excess portions of the gate cap material layer positioned abovethe surface of the layer of insulating material 17. The gate cap layer31 is formed so as to protect the underlying gate materials duringsubsequent processing operations.

Over recent years, due to the reduced dimensions of the transistordevices, the operating speed of the circuit components has beenincreased with every new device generation and the “packing density,”i.e., the number of transistor devices per unit area, in such productshas also increased during that time. Such improvements in theperformance of transistor devices has reached the point where onelimiting factor relating to the operating speed of the final integratedcircuit product is no longer the individual transistor element but theelectrical performance of the complex wiring system that is formed abovethe device level that includes the actual semiconductor-based circuitelements. Typically, due to the large number of circuit elements and therequired complex layout of modern integrated circuits, the electricalconnections of the individual circuit elements cannot be establishedwithin the same device level on which the circuit elements aremanufactured, but require one or more additional metallization layers,which generally include metal-containing lines providing the intra-levelelectrical connection, and also include a plurality of inter-levelconnections or vertical connections, which are also referred to as vias.These vertical interconnect structures comprise an appropriate metal andprovide the electrical connection of the various stacked metallizationlayers.

Furthermore, in order to actually connect the circuit elements formed inthe semiconductor material with the metallization layers, an appropriatevertical contact structure is provided, a first end of which isconnected to a respective contact region of a circuit element, such as agate electrode and/or the drain and source regions of transistors, and asecond end that is connected to a respective metal line in themetallization layer by a conductive via. In some applications, thesecond end of the contact structure may be connected to a contact regionof a further semiconductor-based circuit element, in which case theinterconnect structure in the contact level is also referred to as alocal interconnect. The contact structure may comprise contact elementsor contact plugs having a generally square-like or round shape that areformed in an interlayer dielectric material, which in turn encloses andpassivates the circuit elements. As the critical dimensions of thecircuit elements in the device level decreased, the dimensions of metallines, vias and contact elements were also reduced. In some cases, theincreased packing density mandated the use of sophisticatedmetal-containing materials and dielectric materials in order to reducethe parasitic capacitance in the metallization layers and provide asufficiently high conductivity of the individual metal lines and vias.For example, in complex metallization systems, copper in combinationwith low-k dielectric materials, which are to be understood asdielectric materials having a dielectric constant of approximately 3.0or less, are typically used in order to achieve the required electricalperformance and the electromigration behavior as is required in view ofreliability of the integrated circuits. Consequently, in lower-lyingmetallization levels, metal lines and vias having critical dimensions ofapproximately 100 nm and significantly less may have to be provided inorder to achieve the required packing density in accordance with densityof circuit elements in the device level.

As device dimensions have decreased, the conductive contact elements inthe contact level have to be provided with critical dimensions in thesame order of magnitude. The contact elements typically represent plugs,which are formed of an appropriate metal or metal composition, wherein,in sophisticated semiconductor devices, tungsten, in combination withappropriate barrier materials, has proven to be a viable contact metal.When forming tungsten-based contact elements, typically the interlayerdielectric material is formed first and is patterned so as to receivecontact openings, which extend through the interlayer dielectricmaterial to the corresponding contact areas of the circuit elements. Inparticular, in densely packed device regions, the lateral size of thedrain and source areas and thus the available area for the contactregions is 100 nm and significantly less, thereby requiring extremelycomplex lithography and etch techniques in order to form the contactopenings with well-defined lateral dimensions and with a high degree ofalignment accuracy.

FIG. 2 is a simplistic plan view of an illustrative prior art FinFETdevice 60 that will be referenced to discuss one particular problem asit relates to the formation of contact structures on a FinFET device. Ingeneral, the FinFET device 60 is formed above an active region 61 thatis defined in a semiconductor substrate isolation structure (not shown),such as a shallow trench isolation structure. In the depicted example,the FinFET device 60 is comprised of three illustrative fins 62 and anillustrative gate structure 63. A sidewall spacer 63A and a gate caplayer 63B may be formed so as to encapsulate the gate structure 63. Thefins 62 may be either merged on unmerged. In the depicted example, thefins 62 are unmerged. The fins 62 constitute the source/drain (S/D)regions of the device 60. Also depicted are illustrative source/draincontact structures 64 (which are sometimes referred to as “trenchsilicide” or “TS” or “CA” structures) and a gate contact structure 65(which is sometimes referred to as a “CB” structure). The source/draincontact structures 64 are formed as a line-type structure to insure, tothe extent possible, good contact is achieved with all of the exteriorsurfaces of all of the fins 62, even when assuming a “worst-case”misalignment scenario. The line-type source/drain contact structures 64extend across the entire width 69 of the active region 61 in thegate-width direction 69 of the device 60. The space 66 between the gatecontact structure 65 and the source/drain contact structures 64 must belarge enough such that a short circuit cannot form between the gatecontact structure 65 and one of the line-type source/drain contactstructures 64. In current day devices, the distance 66 may be verysmall, and accordingly, the distance 67 between the active region 61 andthe gate contact structure 65 may be set to be about 30-60 nm. One wayto insure that such a short circuit is not created would be simplyincrease the distance 67, i.e., position the gate contact structure 65farther away from the ends of line-type source/drain contact structures64. Unfortunately, given the drive to ever increase packing densities,such a solution would undesirably increase the “foot-print” of thedevice 60, thereby resulting in an undesirable area consumption penalty.

Device designers are under constant pressure to increase the operatingspeed and electrical performance of transistors and integrated circuitproducts that employ such transistors. Given that the gate length (thedistance between the source and drain regions) on modern transistordevices may be approximately 30-50 nm, and that further scaling isanticipated in the future, device designers have employed a variety oftechniques in an effort to improve device performance, e.g., theabove-noted use of high-k dielectrics, the use of metal gate electrodestructures, the incorporation of work function metals in the gateelectrode structure and the use of channel stress engineering techniqueson transistors (create a tensile stress in the channel region for NMOStransistors and create a compressive stress in the channel region forPMOS transistors). Stress engineering techniques typically involve theformation of specifically made silicon nitride layers that areselectively formed above or in contact with source/drain regions ofappropriate transistors, i.e., a layer of silicon nitride that isintended to impart a tensile stress in the channel region of a NMOStransistor would only be formed above the NMOS transistors. Suchselective formation may be accomplished by masking the PMOS transistorsand then blanket depositing the layer of silicon nitride, or byinitially blanket depositing the layer of silicon nitride across theentire substrate and then performing an etching process to selectivelyremove the silicon nitride from above the PMOS transistors. Conversely,for PMOS transistors, a layer of silicon nitride that is intended toimpart a compressive stress in the channel region of a PMOS transistoris formed above the PMOS transistors. The techniques employed in formingsuch nitride layers with the desired tensile or compressive stress arewell known to those skilled in the art.

However, using such traditional techniques to impart the desired stresson FinFET devices is more problematic. More specifically, due to the useof the line-type source/drain contact structures 64 that extend acrossthe entire width 69 of the of the active region 61 in the gate-widthdirection 69 of the device 60, any stress-inducing layer that is formedon the fins prior to the formation of the line-type source/drain contactstructures 64 will be effectively “cut” by the line-type source/draincontact structures 64, thereby relaxing or limiting the stress in anysuch stress-inducing layer, and its associated ability to impart thedesired stress to the channel region of the transistor device.Accordingly, the use of the above-described line-type source/draincontact structures 64 in FinFET devices makes the formation ofstress-inducing layers using traditional techniques impractical or atleast less effective.

The present disclosure is directed to various methods of formingstressed layers on FinFET semiconductor devices, and the resultingsemiconductor devices, that may avoid, or at least reduce, the effectsof one or more of the problems identified above.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an exhaustive overview of the invention. It is notintended to identify key or critical elements of the invention or todelineate the scope of the invention. Its sole purpose is to presentsome concepts in a simplified form as a prelude to the more detaileddescription that is discussed later.

Generally, the present disclosure is directed to various methods offorming stressed layers on FinFET semiconductor devices, and theresulting semiconductor devices. One method disclosed includes, amongother things, performing at least one etching process so as to define atleast one fin in the substrate, forming a raised isolation structurewith a recess formed therein above the substrate, wherein the recess hasa bottom surface that is positioned below an upper surface of the raisedisolation structure and an interior perimeter surface, and wherein thebottom surface of the recess exposes at least a portion of the at leastone fin, forming a gate structure above the at least one fin, forming astress-inducing material layer above a plurality of source/drain regionsof the device, the raised isolation structure and the gate structure,forming at least one layer of insulating material above thestress-inducing material layer and forming a plurality of post-typesource/drain contact structures that extend through the at least onelayer of insulating material and through the stress-inducing materiallayer, wherein each of the post-type source/drain contact structures isconductively coupled to the at least one fin.

Another illustrative method disclose herein includes, among otherthings, performing at least one etching process so as to define at leastone fin in a semiconductor substrate, forming a raised isolationstructure with a recess above the substrate, wherein the recess has abottom surface that is positioned below an upper surface of the raisedisolation structure and an interior perimeter surface, and wherein thebottom surface of the recess exposes at least a portion of the fin,forming a gate structure above the fin, forming a plurality ofspaced-apart buried fin contact structures within the recess on oppositesides of the gate structure, wherein the buried fin contact structuresare conductively coupled to the fin and have a substantially planarupper surface that is positioned below the upper surface of the raisedisolation structure, forming a stress-inducing material layer on and incontact with the substantially planar upper surface of each of theburied fin contact structures, forming at least one layer of insulatingmaterial above the stress-inducing material layer, the buried fincontact structures and the raised isolation structure, and forming aplurality of source/drain contact structures that extend through thelayer of insulating material and the stress-inducing material layer,wherein each of the source/drain contact structures is conductivelycoupled to one of the plurality of buried fin contact structures.

One illustrative device disclosed herein includes, among other things,at least one fin defined in a semiconductor substrate, a raisedisolation structure with a recess formed therein, wherein the recess hasan upper surface, a bottom surface that is positioned below the uppersurface and an interior perimeter surface, a gate structure positionedaround at least a portion the fin, and a plurality of spaced-apartburied fin contact structures positioned within the recess, wherein eachof the buried fin contact structures is positioned on opposite sides ofthe gate structure and conductively coupled to the fin. In thisembodiment, each of the buried fin contact structures has asubstantially planar upper surface that is positioned below the uppersurface of the raised isolation structure and the device furtherincludes a stress-inducing material layer positioned on and in contactwith the substantially planar upper surface of each of the buried fincontact structures, at least one layer of insulating material positionedabove the stress-inducing material layer, the plurality of buried fincontact structures and the raised isolation structure and a plurality ofsource/drain contact structures that extend through the stress-inducingmaterial layer and the layer of insulating material, wherein each of thesource/drain contact structures is conductively coupled to one of theplurality of buried fin contact structures.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIG. 1A is a perspective view of one illustrative embodiment of a priorart FinFET device;

FIGS. 1B-1F depict one illustrative prior art method of forming a gatestructure of the transistors using a so-called “replacement gate”technique;

FIG. 2 is a simplistic plan view of one illustrative embodiment of aprior art FinFET device with various contact structures formed on thedevice;

FIGS. 3A-3L depict one illustrative method disclosed for formingstressed layers on FinFET semiconductor devices and the resultingsemiconductor devices; and

FIGS. 4A-4H depict another illustrative method disclosed for formingstressed layers on FinFET semiconductor devices and the resultingsemiconductor devices.

While the subject matter disclosed herein is susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and are herein described indetail. It should be understood, however, that the description herein ofspecific embodiments is not intended to limit the invention to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

Various illustrative embodiments of the invention are described below.In the interest of clarity, not all features of an actual implementationare described in this specification. It will of course be appreciatedthat in the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

The present subject matter will now be described with reference to theattached figures. Various structures, systems and devices areschematically depicted in the drawings for purposes of explanation onlyand so as to not obscure the present disclosure with details that arewell known to those skilled in the art. Nevertheless, the attacheddrawings are included to describe and explain illustrative examples ofthe present disclosure. The words and phrases used herein should beunderstood and interpreted to have a meaning consistent with theunderstanding of those words and phrases by those skilled in therelevant art. No special definition of a term or phrase, i.e., adefinition that is different from the ordinary and customary meaning asunderstood by those skilled in the art, is intended to be implied byconsistent usage of the term or phrase herein. To the extent that a termor phrase is intended to have a special meaning, i.e., a meaning otherthan that understood by skilled artisans, such a special definition willbe expressly set forth in the specification in a definitional mannerthat directly and unequivocally provides the special definition for theterm or phrase.

The present disclosure generally relates to various methods of formingstressed layers on FinFET semiconductor devices and the resultingsemiconductor devices. Moreover, as will be readily apparent to thoseskilled in the art upon a complete reading of the present application,the present method is applicable to a variety of devices, including, butnot limited to, logic devices, memory devices, etc., and the methodsdisclosed herein may be employed to form N-type or P-type semiconductordevices. The methods and devices disclosed herein may be employed inmanufacturing products using a variety of technologies, e.g., NMOS,PMOS, CMOS, etc., and they may be employed in manufacturing a variety ofdifferent devices, e.g., memory devices, logic devices, ASICs, etc. Aswill be appreciated by those skilled in the art after a complete readingof the present application, the inventions disclosed herein may beemployed in forming integrated circuit products using a variety ofso-called 3D devices, such as FinFETs. For purposes of disclosure,reference will be made to an illustrative process flow wherein a singleFinFET device 100 is formed. Moreover, the inventions will be disclosedin the context of forming the gate structures using a replacement gate(“gate-last”) processing technique. However, the methods, structures andproducts disclosed herein may be employed where the gate structures ofthe transistors are formed using so-called “gate-first” processingtechniques. Thus, the inventions disclosed herein should not beconsidered to be limited to the illustrative examples depicted anddescribed herein. With reference to the attached figures, variousillustrative embodiments of the methods and devices disclosed hereinwill now be described in more detail.

FIGS. 3A-3L depict one illustrative method disclosed for formingstressed layers on FinFET semiconductor devices and the resultingsemiconductor devices. The illustrative device 100 will be formed in andabove the semiconductor substrate 102. The device 100 may be either anNMOS or a PMOS transistor. Additionally, various doped regions, e.g.,source/drain regions, halo implant regions, well regions and the like,are also not depicted in the attached drawings. The substrate 102 mayhave a variety of configurations, such as the depicted bulk siliconconfiguration. The substrate 102 may also have a silicon-on-insulator(SOI) configuration that includes a bulk silicon layer, a buriedinsulation layer and an active layer, wherein semiconductor devices areformed in and above the active layer. The substrate 102 may be made ofsilicon or it may be made of materials other than silicon. Thus, theterms “substrate” or “semiconductor substrate” should be understood tocover all semiconducting materials and all forms of such materials.

FIGS. 3A-3L present various views of one illustrative embodiment of aFinFET device 100 that may be formed using the methods disclosed herein.The drawings also include a simplistic plan view of the device 100 (inthe upper right corner) that depicts the location where variouscross-sectional views depicted in the following drawings will be taken.More specifically, the view “X-X” is taken along the long axis of a fin(the current transport direction), the view “Y-Y” is a cross-sectionalview that is taken through the source/drain region of the device in adirection that is transverse to the long axis of the fins, and the view“Z-Z” is a cross-sectional view taken through the gate structure of thedevice.

FIG. 3A depicts the device 100 at a point in fabrication wherein severalprocess operations have been performed. FIG. 3A also contains asimplistic plan view of the device 100 showing the formation of theraised isolation region 107. First, a plurality of trenches 102T wereformed in the substrate 102 to thereby define a plurality of fins 106and deeper trenches where a raised isolation region 107 will be formed.The illustrative FinFET device 100 disclosed herein will be depicted asbeing comprised of three illustrative fins 106 with an upper surface106S. However, as will be recognized by those skilled in the art after acomplete reading of the present application, the methods and devicesdisclosed herein may be employed when manufacturing FinFET deviceshaving any number of fins. In one embodiment, the trenches 102T wereformed by performing one or more etching processes through one or morepatterned etch masks (not shown) e.g., a patterned hard mask layer,using known etching techniques. The patterned etch masks may bepatterned using known sidewall image transfer techniques and/orphotolithographic techniques, combined with performing known etchingtechniques. In some applications, a further etching process may beperformed to reduce the width or to “thin” the fins 106, although such athinning process is not depicted in the attached drawings. For purposesof this disclosure and the claims, the use of the terms “fin” or “fins”should be understood to refer to fins that have not been thinned as wellas fins that have been subjected to such a thinning etch process.

The manner in which the illustrative raised isolation region 107 may beformed is well known to those skilled in the art. For example, in oneembodiment, after the trenches are formed, a layer of insulatingmaterial (not separately shown), such as silicon dioxide, wasblanket-deposited on the substrate 102 so as to over-fill the trenches102T with the desired amount of material so as to provide the additionalthickness or height of the raised isolation region 107. A CMP processmay then be performed to planarize the upper surface 107S of the raisedisolation region 107. Next, a patterned etch mask (not show) is formedabove the planarized layer of insulating material to expose a portion ofthe layer of insulating material where it is desired to reduce itsthickness., i.e., in the area between the fins 106. Next, a timed,recess etching process was performed on the exposed portions of thelayer of insulating material to reduce the thickness of the layer ofinsulating material, i.e., to form a recess 107Z in the raised isolationstructure 107 having a recessed bottom surface 107A and an interiorperimeter surface 107X. Effectively this produces a thinner layer of theinsulating material in the bottom of the trenches 102T so as to locallyisolate the fins 106 from one another. This recess etching processexposes the fins 106 to their approximate desired final fin height. Theoverall height of the raised isolation region 107 may vary dependingupon the particular application. In one illustrative embodiment, theraised isolation region 107 is formed such that its upper surface 107Sis positioned approximately 30-50 nm above the level of the uppersurface 106S of the fins 106, as reflected by the dimension 107D.Another illustrative process flow for forming the raised isolationregion 107 includes the following steps: (1) perform the etching processto define the fins 106; (2) over-fill the trenches 102T with silicondioxide; (3) perform a CMP process on the layer of silicon dioxide thatstops on the fins 106; (4) deposit an additional layer of siliconnitride above the polished layer of silicon dioxide; (5) perform anetching process to remove any unwanted fins and define STI trenches; (6)over-fill the STI trenches with silicon dioxide and perform a CMPprocess that stops on the layer of silicon nitride; (7) remove theexposed layer of silicon nitride; and (8) recess the layer of silicondioxide to reveal the desired height of the fins 106.

With continuing reference to FIG. 3A, the overall size, shape andconfiguration of the trenches 102T and fins 106 may vary depending onthe particular application. The depth and width of the trenches 102T mayvary depending upon the particular application. In one illustrativeembodiment, based on current day technology, the depth of the trenches102T may range from approximately 40-100 nm and the width of thetrenches 102T may be about 20-60 nm. In some embodiments, the fins 106may have a final width (at or near the bottom of the fin) within therange of about 5-20 nm. In the illustrative examples depicted in theattached figures, the trenches 102T and fins 106 are all of a uniformsize and shape. However, such uniformity in the size and shape of thetrenches 102T and the fins 106 is not required to practice at least someaspects of the inventions disclosed herein. In the example depictedherein, the trenches 102T are formed by performing an anisotropicetching process that results in the trenches 102T having a schematicallydepicted, generally rectangular configuration. In an actual real-worlddevice, the sidewalls of the trenches 102T may be somewhat inwardlytapered, although that configuration is not depicted in the drawings. Insome cases, the trenches 102T may have a reentrant profile near thebottom of the trenches 102T. To the extent the trenches 102T are formedby performing a wet etching process, the trenches 102T may tend to havea more rounded configuration or non-linear configuration as compared tothe generally rectangular configuration of the trenches 102T that areformed by performing an anisotropic etching process. Thus, the size andconfiguration of the trenches 102T and the fins 106, and the manner inwhich they are made, should not be considered a limitation of thepresent invention. For ease of disclosure, only the substantiallyrectangular trenches 102T and fins 106 will be depicted in subsequentdrawings.

In the example disclosed herein, the FinFET device 100 will be formedusing a replacement gate technique. Accordingly, FIG. 3B depicts thedevice 100 at a point in fabrication wherein a sacrificial gatestructure 120 has been formed above the substrate 102 and the fins 106.Also depicted is an illustrative gate cap layer 126 and sidewall spacers130. The gate cap layer 126 and the sidewall spacers 130 are typicallymade of silicon nitride. At this point in the replacement gate processflow, an anneal process would have already been performed to activatethe implanted dopant materials and repair any damage to the substrate102 due to the various ion implantation processes that were performed.The sacrificial gate structure 120 includes a sacrificial gateinsulation layer 122 and a dummy or sacrificial gate electrode 124. Thevarious components and structures of the device 100 may be formed usinga variety of different materials and by performing a variety of knowntechniques. For example, the sacrificial gate insulation layer 122 maybe comprised of silicon dioxide and the sacrificial gate electrode 124may be comprised of polysilicon. The various layers of material depictedin FIG. 3B, as well as the layers of material described below, may beformed by any of a variety of different known techniques, e.g., achemical vapor deposition (CVD) process, an atomic layer deposition(ALD) process, a thermal growth process, spin-coating techniques, etc.Moreover, as used herein and in the attached claims, the word “adjacent”is to be given a broad interpretation and should be interpreted to coversituations where one feature actually contacts another feature or is inclose proximity to that other feature.

FIG. 3C depicts the device 100 after several process operations wereperformed. First, an optional epi growth process was performed to formadditional semiconductor material 109, e.g., silicon, on the exposedsurfaces of the substrate 102. See views X-X and Y-Y. The generallydiamond-shaped nature of the semiconductor material 109 (see view Y-Y)is due to the way the epi growth process proceeds and the orientation ofthe crystallographic planes in the substrate material. A dashed-line106X reflects the outline of the original fins 106. The epi growthprocess is typically performed to increase the size of the material towhich a conductive contact will later have to be formed. In some cases,if desired, a so-called fin-merger epi growth process is performed suchthat the epi material grown on one fin merges into the epi materialgrown on an adjacent fin. Such merged fins are not depicted in thedrawings. Thereafter, a thin etch stop liner 132 (e.g., 2-3 nm) wasformed above the entire device 100. The etch stop liner 132 may becomprised of a variety of materials, e.g., silicon nitride, and it maybe formed by performing a conformal ALD or CVD process.

FIG. 3D depicts the device 100 after several process operations wereperformed. First, a layer of insulating material 111 (e.g., silicondioxide) was formed above the device 100 using traditional depositiontechniques. Then, one or more planarization processes (e.g., CMP) wereperformed on the layer of insulating material 111 such that the uppersurface 111S of the layer of insulating material 111 is substantiallyeven with the upper surface 124S of the sacrificial gate electrode 124.Importantly, this planarization process exposes the upper surface 124Sof the sacrificial gate electrode 124 such that it can be removed. Inone illustrative embodiment, the planarization process may be a chemicalmechanical planarization (CMP) process that stops on the sacrificialgate electrode 124.

FIG. 3E depicts the device 100 after one or more wet or dry etchingprocesses were performed to remove the sacrificial gate electrode 124and the sacrificial gate insulation layer 122 to thereby define a gatecavity 136 where a replacement gate structure will subsequently beformed for the device 100. Typically, the sacrificial gate insulationlayer 122 is removed as part of the replacement gate technique, asdepicted herein. However, the sacrificial gate insulation layer 122 maynot be removed in all applications. Even in cases where the sacrificialgate insulation layer 122 is intentionally removed, there will typicallybe a very thin native oxide layer (not shown) that forms on the surface106S of the fins within the gate cavity 136. To the extent that theremoval of the sacrificial gate structure 120 causes any consumption ofthe isolation region 107, such consumption is not depicted in theattached drawings.

FIG. 3F depicts the device 100 after several process operations wereperformed. First, a pre-clean process was performed in an attempt toremove all foreign materials from within the gate cavity 136 prior toforming the various layers of material that will become part of thereplacement gate structure 133. Thereafter, several known processingoperations were performed to form a schematically depicted replacementgate structure 133 in the gate cavity 136. The replacement gatestructure 133 depicted herein is intended to be representative in natureof any type of gate structure that may be employed in manufacturingintegrated circuit products using so-called gate-last (replacement-gate)manufacturing techniques. The replacement gate structure 133 typicallycomprises a high-k (k value greater than 10) gate insulation layer (notindividually shown), such as hafnium oxide, one or more metal layers(not individually shown) (e.g., layers of titanium nitride or TiAlCdepending upon the type of transistor device being manufactured), and abulk conductive material layer (not individually shown), such astungsten or aluminum. Typically, the various layers of material thatwill be present in the replacement gate structure 133 are sequentiallydeposited in the gate cavity 136 and above the layer of insulatingmaterial 111 and one or more CMP processes are performed to removeexcess portions of the gate materials positioned outside of the gatecavity 136. Then, one or more etching processes were performed to removeupper portions of the various materials within the cavity 136 so as toform the replacement gate structure 133 and to form a recess above thereplacement gate structure 133. Then, a gate cap layer 140 was formed inthe recess above the recessed gate materials. The gate cap layer 140 istypically comprised of silicon nitride and it may be formed bydepositing a layer of gate cap material so as to over-fill the recessformed in the gate cavity 136 above the replacement gate structure 133and thereafter performing a CMP process to remove excess portions of thegate cap material layer positioned above the surface of the layer ofinsulating material 111. The gate cap layer 140 is formed so as toprotect the underlying gate materials during subsequent processingoperations.

FIG. 3G depicts the device 100 after several process operations wereperformed. First, an etching process was performed to remove the layerof insulating material 111. Thereafter, an etching process was performedto remove the etch stop layer 132. In some embodiments, the removal ofthe layer of insulating material 111 and the etch stop layer 132 may beaccomplished in a single process chamber and changing the etchchemistries as needed. Then, a traditional silicidation process wasperformed to form metal silicide regions 110 on the surfaces of the episemiconductor material 109 (see views X-X and Y-Y). In general, such asilicidation process typically involves depositing a layer of metal (notshown), such as nickel, cobalt, titanium, platinum, etc., or acombination of such materials, such that it contacts the exposedportions of the epi semiconductor material 109 (or on the fins 106 if noepi material 109 is grown). Then, a first anneal process is performed ata temperature that falls within the range of about 220-300° C. such thatthe layer of metal reacts with the silicon in the silicon-containingregions contacted by the layer of metal to thereby form a relativelyhigher resistance form of metal silicide. Next, portions of the layer ofmetal that did not react with the epi semiconductor material 109 duringthe first anneal process are removed by performing a standard strippingprocess. After the removal of the unreacted portions of the layer ofmetal, a second anneal process is performed on the device 100 at atemperature that falls within the range of about 400-500° C. so as toconvert the relatively higher resistance silicide region into therelatively lower resistance metal silicide region 110. By forming themetal silicide regions 110 after the replacement gate structure 133 wasformed (see FIG. 3F), the metal silicide region 110 is not exposed tothe relatively high processing temperatures that may be associated withthat activity. That is, a metal silicide material usually becomesunstable and its resistance increases if it is exposed to annealtemperatures greater than about 700° C.

FIG. 3H depicts the device 100 after a layer of conductive material 150,e.g., a metal, was blanket-deposited on the device 100. The layer ofconductive material 150 will be the material from which a buried fincontact structure will be formed, as described more fully below. In oneillustrative embodiment, the layer of conductive material 150 may becomprised of tungsten, aluminum, copper, etc., and it may be formed byperforming a PVD or a CVD process. Additionally, prior to the formationof the layer of conductive material 150, one or more barrier layers (notdepicted) may be deposited on the product. In one illustrative example,the methods disclosed herein may include depositing a liner, e.g., Ti,TiN, followed by blanket-depositing a conductive material, such astungsten. Thereafter, a CMP process may be performed to planarize theupper surface of the layer of conductive material 150.

Next, as shown in FIG. 3I, a timed, recess etching process was performedon the layer of conductive material 150 to reduce its thickness suchthat its upper surface 150S is positioned approximately level with orabout 3-5 nm below (i.e., below the level of) the upper surface 107S ofthe raised isolation region 107. This process operation results in theformation of a buried fin contact structure 150R that is positioned inthe recess 107Z formed in the raised isolation structure 107. Note thatthe buried fin contact structure 150R is fully recessed relative to theupper surface 107S of the raised isolation region 107. FIG. 3I alsocontains a simplistic plan view of the device 100 showing the formationof the buried fin contact structures 150R within the recess 107Z of theraised isolation region 107 on opposite sides of the gate structure.Also note that the exterior perimeter surfaces 150X engage the interiorperimeter surfaces 107X of the recess 107Z, and in the depicted example,engage the outer sidewall spacers 130.

FIG. 3J depicts the device 100 after several process operations wereperformed. First, a layer of stress-inducing material layer 149 wasformed above the device 100. Thereafter, a layer of insulating material152 (e.g., silicon dioxide) was formed above the stress-inducingmaterial layer 149 using traditional deposition techniques. Then, one ormore planarization processes (e.g., CMP) were performed on the layer ofinsulating material 152. The stress-inducing material layer 149/layer ofinsulating material 152, along with the raised isolation region 107,effectively encapsulates the buried fin contact structure 150R. Thestress-inducing material layer 149 may be comprised of a variety ofdifferent materials, e.g., silicon nitride, ZnS—SiO₂, etc., it may beformed to any desired thickness, e.g., (3-15 nm), it may be formed usinga variety of techniques, e.g., CVD, and it may be formed with either atensile stress (for an NMOS device) or a compressive stress (for a PMOSdevice). The magnitude of the stress present in the stress\-inducingmaterial layer 149 may vary depending upon the particular application,e.g., 0.1-2 GPa (tensile) or 0.1-3 GPa (compressive). The layer ofinsulating material 152 (e.g., silicon dioxide) was formed above thestress-inducing material layer 149 using traditional depositiontechniques.

FIG. 3K depicts the device 100 after several process operations wereperformed to form a conductive source/drain contact structure 154 toeach of the buried fin contact structures 150R and to form the gatecontact structure 156 that is conductively coupled to the replacementgate structure 133, i.e., to the conductive gate materials that are partof the replacement gate structure 133. Typically, this processingsequence involves performing one or more etching processes through oneor more etch mask layers (not shown) on the exposed portions of thelayer of insulating material 152, the stress-inducing material layer 149and/or on the gate cap layer 140 to define contact openings 154A/156Afor the various conductive structures. The source/drain contactstructures 154 and the gate contact structure 156 may be of any desiredcross-sectional configuration when viewed from above, e.g., square,rectangular, round, etc. As depicted, the source/drain contactstructures 154 are conductively coupled to the buried fin contactstructures 150R while the gate contact structure 156 is conductivelycoupled to the replacement gate structure 133. The source/drain contactstructures 154 and the gate contact structure 156 are intended to beschematic and representative in nature, as they may be formed using anyof a variety of different conductive materials and by performingtraditional manufacturing operations. The contact structures 154/156 mayalso contain one or more barrier layers (not depicted). In oneillustrative example, the contact structures 154/156 may be formed bydepositing a liner, e.g., Ti, TiN, followed by overfilling the contactopenings 154A/156A with a conductive material, such as tungsten.Thereafter, a CMP process may be performed to planarize the uppersurface of the layer of insulating material 152, which results in theremoval of excess portions of the liner and the tungsten positionedabove the layer of insulating material 152 outside of the openings154A/154B and the formation of the contact structures 154/156. Notethat, in one embodiment, the thickness 156D of the replacement gatestructure 133 above the raised isolation region 107 where the gatecontact structure 156 will make contact may be on the order of about 20nm.

FIG. 3L is a simplistic plan view of one embodiment of a FinFET device100 disclosed herein after the formation of the illustrative contactstructures 154/156 with the layer of insulating material 152 removed. Ascan be seen, the stress-inducing material layer 149 is positioned on theburied fin contact structure 150R that is positioned within the recess107Z of the raised isolation region 107. Note that, due to the fact thatthe buried fin contact structure 150R is conductively coupled to all ofthe fins 106, the source/drain contact structure 154 may be a singlepost-type source/drain contact structure, as compared to the typicalprior art line-type source/drain contact structures 64 shown in FIG. 2.Accordingly, the distance between the source/drain contact structure 154and the gate contact structure 156 may be increased relative to thatdistance in prior art devices and, correspondingly, the chances of thegate contact structure 156 shorting with the source/drain contactstructures 154 is reduced. The structure of the device 100 herein alsomeans that the distance 118 between the active area and the gate contactstructure 156 may be reduced as compared to prior art structures. Forexample, in one illustrative embodiment, the distance 118 between theactive region and the gate contact structure 156 may be about 10-30 nm.Accordingly, using the methods and devices disclosed herein, the packingdensities on integrated circuit products using such devices 100 may bereduced relative to corresponding prior art products, thereby desirablydecreasing the “foot-print” of the device 100. In particular, note that,in the devices disclosed herein, the post-type source/drain contactstructures 154 do not extend across the entire width of the activeregion in the gate-width direction 119 of the device 100. Rather, theends of the post-type source/drain contact structures 154 stop wellshort of the edges of the active region. In one embodiment, thedimension (length or diameter) of the post-type source/drain contactstructures 154 in the gate width direction 119 may be about 10-80% ofthe overall width of the active region in the gate width direction 119of the device 100. In the depicted example, a single post-typesource/drain contact structure 154 is depicted as being formed toestablish electrical contact to the source/drain regions. However, ifdesired, more than one of the post-type source/drain contact structures154 may be formed on each of the source/drain regions. For example, twoof the post-type source/drain contact structures 154 may be formed so asto contact the buried fin contact structure 150R above each of thesource/drain regions of the device. It is also important to note that,due to the use of the post-type source/drain contact structures 154, thestress-inducing material layer 149 is not “cut” as it would be usingtraditional line-type source/drain contact structures, such as theline-type source/drain contact structures 64 depicted in FIG. 2. As aresult, the stress present in the stress-inducing material layer 149 maybe more efficiently transferred to the channel region of the device 100.

FIGS. 4A-4G depict another illustrative method disclosed for formingstressed layers on FinFET semiconductor devices and the resultingsemiconductor devices. FIG. 4A depicts the device 100 at a point infabrication that corresponds to that shown in FIG. 3C above, i.e., thesacrificial gate structure 120, the epi semiconductor material 109 andthe etch stop layer 132 have been formed as described above.

FIG. 4B depicts the device 100 after several process operations wereperformed. First, the above-described insulating material 111 (e.g.,silicon dioxide) was formed above the device 100 using traditionaldeposition techniques. Then, one or more planarization processes (e.g.,CMP) were performed on the layer of insulating material 111 such thatits upper surface was substantially planar. Next, an etch-back processwas performed to recess the upper surface 111S of the layer ofinsulating material 111 a desired amount relative to the upper surface124S of the sacrificial gate structure 124, e.g., a distance of about10-20 nm. Then, a sacrificial material layer 135, e.g., silicon nitride(with a final thickness after CMP of about 5-10 nm) wasblanket-deposited on the device 100. One or more CMP processes were thenperformed so as to remove all materials positioned above the uppersurface 1245 of the sacrificial gate electrode 124. Importantly, theseoperations result in the exposure of the sacrificial gate electrode 124so that it can be removed. In some cases, the sacrificial siliconnitride material 135 may not need to be formed as indicated. Additionalsilicon dioxide material could have been formed in lieu of thesacrificial silicon nitride material 135, as the purpose of thesacrificial silicon nitride material 135 is to prevent excessive loss ofthe silicon dioxide material during subsequent processing operations. Ifdesired, the layers of material may be formed as described in U.S.patent application Ser. No. 13/654,717, entitled “Facilitating GateHeight Uniformity and Inter-layer Dielectric Protection,” which ishereby incorporated by reference in its entirety.

FIG. 4C depicts the device 100 after one or more wet or dry etchingprocesses were performed to remove a portion, but not all, of thesacrificial gate structure 120, such that the now-recessed upper surface120R of the recessed sacrificial gate structure is positioned at a levelthat is approximately even with the upper surface 107S or below (i.e.,at a level below) the upper surface 107S of the raised isolation region107 by a distance of about 3-20 nm. This etching process results in thedefinition of a partial gate cavity, as not all of the sacrificial gatestructure has been removed.

FIG. 4D depicts the device 100 after a timed etching process wasperformed to remove the exposed portions of the sacrificial gateinsulation layer 122 and to recess portions of the raised isolationregion 107 that will underlie the replacement gate structure. Note therecessed surface 107R of the raised isolation region 107 in view Z-Z. Inone embodiment, the now-recessed surface 107R of the raised isolationregion 107 is positioned below the upper surface 120R of the recessedsacrificial gate structure by a distance of about 10-50 nm.

FIG. 4E depicts the device 100 after one or more wet or dry etchingprocesses were performed to remove the remaining portions of therecessed sacrificial gate structure, i.e., any remaining portion of thesacrificial gate electrode 124 and the sacrificial gate insulation layer122, to thereby define the full gate cavity 136 where the replacementgate structure 133 will subsequently be formed for the device 100.

FIG. 4F depicts the device 100 after several process operations wereperformed. First, the materials for the above-described replacement gatestructure 133 were formed in the gate cavity 136. As part of thatprocess, and as described above, one or more etching processes wereperformed to remove the upper portions of the various materials withinthe cavity 136 so as to form the replacement gate structure 133 and toform a recess above the replacement gate structure 133. Then, the gatecap layer 140 was formed in the recess above the recessed gatematerials. During the CMP processes performed in forming the gate caplayer 140, the sacrificial material layer 135 was cleared from above thesurface of the layer of insulating material 111.

FIG. 4G depicts the device 100 after the layer of insulating material111 was removed and after the above-described buried fin contactstructure 150R and the stress-inducing material layer 149 were formed.

FIG. 4H depicts the device after the above-described layer of insulatingmaterial 152, source/drain contact structures 154 and the gate contactstructure 156 have been formed on the device 100. Note that, due to therecessing of the raised isolation region 107, the thickness of thereplacement gate structure 133 where contact is made by the gate contactstructure 156 is greater than that for the device shown in FIG. 3K(compare the distance 156D with the distance 156X). In one embodiment,the thickness 156X of the replacement gate structure 133 above therecessed surface 107R of the raised isolation region 107 where the gatecontact structure 156 will make contact may be on the order of about 40nm or more.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. For example, the process steps set forth above may beperformed in a different order. Furthermore, no limitations are intendedto the details of construction or design herein shown, other than asdescribed in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Note that the use of terms, such as “first,” “second,”“third” or “fourth” to describe various processes or structures in thisspecification and in the attached claims is only used as a shorthandreference to such steps/structures and does not necessarily imply thatsuch steps/structures are performed/formed in that ordered sequence. Ofcourse, depending upon the exact claim language, an ordered sequence ofsuch processes may or may not be required. Accordingly, the protectionsought herein is as set forth in the claims below.

What is claimed:
 1. A method of forming a FinFET transistor above asemiconductor substrate, said transistor comprising at least one fin anda plurality of source/drain regions, wherein the method comprises:performing at least one etching process so as to define said at leastone fin in said substrate; after defining said at least one fin in saidsubstrate, forming a raised isolation structure with a recess formedtherein above said substrate, wherein said recess has a bottom surfacethat is positioned below an upper surface of said raised isolationstructure and an interior perimeter surface, and wherein said bottomsurface of said recess exposes at least a portion of said at least onefin; after forming said raised isolation structure above said substrate,forming a gate structure above said at least one fin; forming astress-inducing material layer above said plurality of source/drainregions of said device, said raised isolation structure and said gatestructure; forming at least one layer of insulating material above saidstress-inducing material layer; and forming a plurality of post-typesource/drain contact structures that extend through said at least onelayer of insulating material and through said stress-inducing materiallayer, wherein each of said post-type source/drain contact structures isconductively coupled to said at least one fin.
 2. The method of claim 1,wherein, prior to forming said stress-inducing material layer, themethod comprises forming a plurality of spaced-apart buried fin contactstructures within said recess, said buried fin contact structures beingformed in said recess on opposite sides of said gate structure, whereineach of said buried fin contact structures is conductively coupled tosaid at least one fin and have a substantially planar upper surface thatis positioned level with or below said upper surface of said raisedisolation structure, and thereafter forming said stress-inducingmaterial layer on and in contact with said upper surface of said buriedfin contact structure.
 3. The method of claim 1, wherein forming saidgate structure above said at least one fin comprises performing one of agate-last or a gate-first processing sequence to form said gatestructure.
 4. The method of claim 1, wherein said stress-inducingmaterial layer is formed with one of a tensile stress or a compressivestress.
 5. The method of claim 2, wherein forming said plurality ofburied fin contact structures within said recess comprises: depositing alayer of conductive material above said raised isolation structure so asto over-fill said recess; and performing a timed recess etching processon said layer of conductive material so as to clear said conductivematerial from above said upper surface of said raised isolationstructure and to define said buried fin contact structures having saidsubstantially planar upper surface that is positioned level with orbelow said upper surface of said raised isolation structure.
 6. Themethod of claim 2, wherein said gate structure is a sacrificial gatestructure and wherein, prior to forming said plurality of spaced-apartburied fin contact structures, the method further comprises: performingat least one second etching process to remove a portion of at least asacrificial gate electrode of said sacrificial gate structure so as tothereby define a recessed sacrificial gate structure and to define apartial gate cavity, wherein said at least one second etching process isperformed such that an upper surface of said recessed sacrificial gatestructure is positioned at a level below a level of said upper surfaceof said raised isolation structure; with said recessed sacrificial gatestructure in position, performing at least one third etching process toreduce a thickness of a portion of said raised isolation structure in anarea under said partial gate cavity such that an upper surface of saidreduced thickness portion of said raised isolation structure ispositioned at a level that is below said upper surface of said recessedsacrificial gate electrode; after performing said at least one thirdetching process, removing at least said recessed sacrificial gatestructure so as to define a full gate cavity; and forming a replacementgate structure in said full gate cavity.
 7. The method of claim 2,wherein forming said stress-inducing material layer comprises formingsaid stress-inducing material layer on and in contact with substantiallythe entire planar upper surface of each of said buried fin contactstructures.
 8. A method of forming a FinFET transistor above asemiconductor substrate, said transistor comprising at least one fin,wherein the method comprises: performing at least one etching process soas to define said at least one fin in said substrate; after definingsaid at least one fin in said substrate, forming a raised isolationstructure with a recess formed therein above said substrate, whereinsaid recess has a bottom surface that is positioned below an uppersurface of said raised isolation structure and an interior perimetersurface, and wherein said bottom surface of said recess exposes at leasta portion of said at least one fin; after forming said raised isolationstructure above said substrate, forming a gate structure above said atleast one fin; forming a plurality of spaced-apart buried fin contactstructures within said recess, said buried fin contact structures beingformed in said recess on opposite sides of said gate structure, whereineach of said buried fin contact structures is conductively coupled tosaid at least one fin and have a substantially planar upper surface thatis positioned level with or below said upper surface of said raisedisolation structure; forming a stress-inducing material layer on and incontact with said substantially planar upper surface of each of saidburied fin contact structures; forming at least one layer of insulatingmaterial above said stress-inducing material layer, said plurality ofburied fin contact structures and said raised isolation structure; andforming a plurality of source/drain contact structures that extendthrough said stress-inducing material layer and said at least one layerof insulating material, wherein each of said plurality of source/draincontact structures is conductively coupled to one of said plurality ofburied fin contact structures.
 9. The method of claim 8, wherein each ofsaid buried fin contact structures comprises an outer perimeter surface,and wherein said outer perimeter surface of each of said buried fincontact structures contacts at least a portion of said interiorperimeter surface of said recess in said raised isolation structure anda sidewall spacer formed adjacent said gate structure.
 10. The method ofclaim 8, wherein said stress-inducing material layer is formed on and incontact with an entirety of said upper surface of each of said buriedfin contact structures.
 11. The method of claim 8, wherein forming saidplurality of buried fin contact structures within said recess comprises:depositing a layer of conductive material above said raised isolationstructure so as to over-fill said recess; and performing a timed recessetching process on said layer of conductive material so as to clear saidconductive material from above said upper surface of said raisedisolation structure and to define said buried fin contact structureshaving said upper surface that is positioned level with or below saidupper surface of said raised isolation structure.
 12. The method ofclaim 8, wherein said gate structure is a sacrificial gate structure andwherein, prior to forming said plurality of spaced-apart buried fincontact structures, the method further comprises: performing at leastone second etching process to remove a portion of at least a sacrificialgate electrode of said sacrificial gate structure so as to therebydefine a recessed sacrificial gate structure and to define a partialgate cavity, wherein said at least one second etching process isperformed such that an upper surface of said recessed sacrificial gatestructure is positioned at a level below a level of said upper surfaceof said raised isolation structure; with said recessed sacrificial gatestructure in position, performing at least one third etching process toreduce a thickness of a portion of said raised isolation structure in anarea under said partial gate cavity such that an upper surface of saidreduced thickness portion of said raised isolation structure ispositioned at a level that is below said upper surface of said recessedsacrificial gate electrode; after performing said at least one thirdetching process, removing at least said recessed sacrificial gatestructure so as to define a full gate cavity; and forming a replacementgate structure in said full gate cavity.
 13. The method of claim 8,wherein said gate structure extends continuously across said at leastone fin and at least a portion of said raised isolation structure. 14.The method of claim 1, wherein said gate structure extends continuouslyacross said at least one fin and at least a portion of said raisedisolation structure.
 15. A method of forming a FinFET transistor above asemiconductor substrate, said transistor comprising at least one fin anda plurality of source/drain regions, wherein the method comprises:performing at least one etching process so as to define said at leastone fin in said substrate; forming a raised isolation structure with arecess formed therein above said substrate, wherein said recess has abottom surface that is positioned below an upper surface of said raisedisolation structure and an interior perimeter surface, and wherein saidbottom surface of said recess exposes at least a portion of said atleast one fin; forming a gate structure above said at least one fin;forming a plurality of spaced-apart buried fin contact structures withinsaid recess and on opposite sides of said gate structure, each of saidplurality of spaced-apart buried fin contact structures beingconductively coupled to said at least one fin and having a substantiallyplanar upper surface that is positioned level with or below said uppersurface of said raised isolation structure, wherein forming saidplurality of spaced-apart buried fin structures comprises: depositing alayer of conductive material above said raised isolation structure so asto over-fill said recess; and performing a timed recess etching processon said layer of conductive material so as to clear said conductivematerial from above said upper surface of said raised isolationstructure and to define said plurality of spaced-apart buried fincontact structures; forming a stress-inducing material layer above saidplurality of source/drain regions of said device, said raised isolationstructure and said gate structure, wherein said stress-inducing materiallayer is formed on and in contact with said upper surface of each ofsaid plurality of spaced-apart buried fin contact structures; forming atleast one layer of insulating material above said stress-inducingmaterial layer; and forming a plurality of post-type source/draincontact structures that extend through said at least one layer ofinsulating material and through said stress-inducing material layer,wherein each of said post-type source/drain contact structures isconductively coupled to said at least one fin.
 16. A method of forming aFinFET transistor above a semiconductor substrate, said transistorcomprising at least one fin, wherein the method comprises: performing atleast one etching process so as to define said at least one fin in saidsubstrate; forming a raised isolation structure with a recess formedtherein above said substrate, wherein said recess has a bottom surfacethat is positioned below an upper surface of said raised isolationstructure and an interior perimeter surface, and wherein said bottomsurface of said recess exposes at least a portion of said at least onefin; forming a gate structure above said at least one fin; forming aplurality of spaced-apart buried fin contact structures within saidrecess and on opposite sides of said gate structure, each of saidplurality of spaced-apart buried fin contact structures beingconductively coupled to said at least one fin and having a substantiallyplanar upper surface that is positioned level with or below said uppersurface of said raised isolation structure, wherein forming saidplurality of spaced-apart buried fin structures comprises: depositing alayer of conductive material above said raised isolation structure so asto over-fill said recess; and performing a timed recess etching processon said layer of conductive material so as to clear said conductivematerial from above said upper surface of said raised isolationstructure and to define said plurality of spaced-apart buried fincontact structures; forming a stress-inducing material layer on and incontact with said substantially planar upper surface of each of saidburied fin contact structures; forming at least one layer of insulatingmaterial above said stress-inducing material layer, said plurality ofburied fin contact structures and said raised isolation structure; andforming a plurality of source/drain contact structures that extendthrough said stress-inducing material layer and said at least one layerof insulating material, wherein each of said plurality of source/draincontact structures is conductively coupled to one of said plurality ofburied fin contact structures.